top of page

Micro-Architectural support for High Availability of NoC-based MP-SoC

38th Digital Avionics Systems Conference in San Diego, USA 2019

Abstract: In this paper, we focus on increasing the availability of Multi-Processor System on Chip (MPSoC) for executing user applications, even when some components of the system are faulty. A Network-on-Chip (NoC) provides high bandwidth communication substrate for the multitude of components/modules insuch MP-SoCs. Health of such MP-SoC, and hence its availability, is largely dependent on the health of the NoC. We consider an NoC comprising a bidirectional toroidal mesh interconnection of routers. We use a distributed built-in-self-test to identify faulty communication links. We use information so obtained to determine healthy subsystems that can be made available for executing user applications. This feature is key for enhancing availability of MP-SoCs. We realize this feature as a micro-architectural enhancement inMP-SoC that incurs an insignificant hardware overheadof less than 2%. Latency incurred for analyzing availability of MP-SoC is also insignificant. We functionally validate our proposal by emulating the system on aFPGA device and demonstrate increase in availability of the MP-SoC.

Experimental Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architecture

37th Digital Avionics Systems Conference in London, UK 2018

Abstract: Multi-core processors pervade numerous industries but they still represent a challenge for the aerospace industry, where strong certification of every components is required. Oneway to make them enforce safety-criticality constraints is to ensure reallocation of critical tasks on the chip when they are affected by hardware faults. This paper describes and compares different models of a task reallocation problem for a reconfigurable multi-core architecture. It also presents the first version of the macroscopic model made of Raspberry Pi that was built to represent the multi-core architecture and to test the task allocation algorithm on an actual system, showing the increased robustness that the reallocation algorithm enables while cores are made faulty.

Task allocation of safety-critical applications on reconfigurable multi-core architectures

36th Digital Avionics Systems Conference in Florida, USA 2017

Abstract: In the aerospace industry, the highest criticality standard is required for the certification of avionics systems. A multi-core processor with reconfiguration capabilities where safety-critical applications are reallocated once they are affected by faults is one efficient way to enforce such criticality constraints. This paper presents a new model of a task reallocation problem for a reconfigurable multi-core architecture, which allows an execution of lower priority applications when the resources for executing the higher application are insufficient. Furthermore, it provides an implementation of an actual cyber-physical system: the control of a propulsive system with three redundant controllers. In addition to the fault injection mechanisms, a fault recovery capability and a fault detection system based on a majority rule voter are included.

REFRESH: REDEFINE for Face Recognition using SURE Homogeneous Cores

IEEE Transactions on Parallel and Distributed Systems (Vol. 27, pp. 3602-3616, 2016)

Abstract: In this paper we present design and analysis of a scalable real-time Face Recognition (FR) module to perform 450 recognitions per second. We introduce an algorithm for FR, which is a combination of Weighted Modular Principle Component Analysis and Radial Basis Function Neural Networks. This algorithm offers better recognition accuracy in various practical conditions than algorithms used in existing architectures for real-time FR. To meet real-time requirements, a Scalable Parallel Pipelined Architecture (SPPA) is developed by realizing the above FR algorithm as independent parallel streams and sub-streams of computations. SPPA is capable of supporting large databases maintained in external (DDR) memory. By casting the computations in a stream into hardware, we present the design of a Scalable Unit for Region Evaluation (SURE) core. Using SURE cores as computer elements in a massively parallel CGRA, like REDFINE, we provide a FR system on REDEFINE called REFRESH. We report FPGA and ASIC synthesis results for SPPA and REFRESH. Through analysis using these results, we show that excellent scalability and added programmability in REFRESH makes it a flexible and favorable solution for real-time FR.

REDEFINE: Runtime Reconfigurable Polymorphic ASIC

ACM Transactions on Embedded Computing Systems (Vol. 9, No. 2, Article 11, Sep 2009)

Abstract: Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a “future-proof” custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor.

REDEFINE - case for WCET friendly hardware acclerators for real time applications

Abstract: REDEFINE is a distributed dynamic dataƒflow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). ‘is paper dwells on the ƒflexibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.

Compilers, Architecture & Synthesis for Embedded Systems (CASES) in Seoul, South Korea 2017

Resources: List
bottom of page