REDEFINE™ stands in a class of its own, with dynamic instantiations of diverse Domain Specific Architectures on the same silicon. For the first time, you get:
the efficiency and security of customised hardware
the ability to be reconfigured at runtime for a new set of tasks
seamless scalability from 16-cores to 256-cores (now) and upto 4K-cores without the need for software changes.
REDEFINE™ is a many-core SoC platform, in which domain specific architectures (DSAs) for mixed critical application tasks are instantiated on demand upon an event. The market verticals that stands to benefit from the REDEFINE™ SoC are Avionics, Automotives, and 5G/6G Telecom. Similarly, REDEFINE™ will feature as an accelerator for a horizontal market spanning applications for high performance Big Data Analytics, Genome Analytics, Augmented Reality and Virtual Reality, Large Scale Scientific Simulations, immersive gaming and visualizations.
The REDEFINE™ architecture offers seamless scalability from 16-cores to 4K-cores without any software changes. Multiple, and diverse accelerators are realized on REDEFINE™'s SoC as diverse DSAs, all of them co-existing on the same chip. Different configurations of REDEFINE™ are toroidal mesh interconnections of base REDEFINE™ nodes.
A Base REDEFINE™ Compute Node with 4 cores and 512 KB on-chip memory, delivers a peak performance of 8 GFLOPS @1 GHz, and 16 GOPS with 16-bit integer units.
16-core REDEFINE™ with 2 MB on-chip memory, delivers a peak performance of 32 GFLOPS/64 GOPS @1 GHz.
64-core REDEFINE™ with 8 MB on-chip memory, delivers a peak performance of 128 GFLOPS/256 GOPS @1 GHz.
256-core REDEFINE™ with 32 MB on-chip memory, delivers a peak performance of 512 GFLOPS/1 TOPS @1 GHz.
With technology constantly evolving, rarely is an innovation truly disruptive. REDEFINE™'s reconfigurable silicon cores give you all the benefits of specialized ASICs in terms of latency, efficiency and power while also being functionally reconfigurable.
Emerging applications of smart grids, avionics, autonomous vehicles, network processing for next generation telecom, collaborative robots in Industry 4.0, and online data analytics are setting the requirements for high performance computing on the core and edge. These applications involve performing specific tasks (often disparate in nature) upon an event, where the event is either an external stimulus or a stimulus generated from within a task to trigger other tasks. Unlike traditional real-time applications, where dedicated computing platforms would perform such time-critical tasks, there is a paradigm shift to integrated heterogeneous accelerators on a single processing platform. However, the promise of many advantages such integrated systems can bring to the fore is fraught with challenges which are rooted both in hardware and software. For instance, in autonomous vehicles, a subset of the tasks that needs to run in parallel could include tasks for deep learning, computer vision, sensor fusion etc., each of which come with different performance requirements. This is something that will be experienced across applications for next generation avionics, 5G/6G network processing, and for performing analytics on unstructured data.
Depending on the performance requirements for individual tasks from the application domains mentioned earlier, there are either software-only or hardware-only solutions. Software-only solutions are realized on multi-core CPUs, or GPUs, whereas, hardware-only solutions are either on dedicated chipsets or on FPGAs. These solutions are power inefficient, and cannot easily scale. Additionally, for critical application domains, security cannot be easily ensured in any of the prevalent solution methods. When it comes to reactive applications, it is difficult to come up with parallel implementations on multi-cores with deterministic performance. Further, none of the existing solutions that rely on real-time OS can handle mixed critical data parallel and task parallel applications simultaneously. Real-time OS are known to impose severe limits on the number of tasks that can be simultaneously supported, suffer from problems of heavy use of system resources, complex algorithms for task management, device drivers and interrupt handling, and thread priority. To a large extent we owe all these overheads to the control flow model of execution adopted for processing.
Morphing Machines’ REDEFINE™ System-on-Chip (SoC) is a many-core platform, that brings you the benefit of multiple domain specific architectures (DSAs) on a chip. It is through instantiations of such DSAs on demand for mixed critical tasks/applications, that REDEFINE exploits multi-level, and multi-scale parallelism in the DSAs. The technology driving REDEFINE™ is the unique combination of its execution model (for reactive computing), runtime reconfiguration (for the creation of DSAs), and many-core processing (for high performance).
Interested in details of the REDEFINE™ execution model, the programming abstraction for creation of DSAs, and the compilation flow for realizing applications?